UR=Val_0x0
Software Reset Register
| UR | UART Reset This bit asynchronously resets the UART and synchronously removes the reset assertion. Both PCLK and SCLK will be reset. 0 (Val_0x0): No UART reset 1 (Val_0x1): UART reset |
| RFR | Rx FIFO Reset This is a shadow bit for the UART_FCR[RFIFOR] bit. It is used to remove the burden on software having to store previously written UART_FCR values just to reset the Rx FIFO. This resets the control portion of the Rx FIFO and treats the FIFO as empty. This will also deassert the DMA Rx request and single signals when additional DMA handshaking signals are selected. Note that this bit is self-clearing. |
| XFR | Tx FIFO Reset This is a shadow bit for the UART_FCR[XFIFOR] bit. It is used to remove the burden on software having to store previously written UART_FCR values just to reset the Tx FIFO. This resets the control portion of the Tx FIFO and treats the FIFO as empty. This will also deassert the DMA Tx request and single signals when additional DMA handshaking signals are selected. Note that this bit is self-clearing. |